The present technique relates to an apparatus and method for handling page invalidate requests in an address translation cache.
It is known to provide data processing systems which incorporate an address translation cache, such as a translation lookaside buffer (TLB), to store address translation data relating to the translation of virtual addresses to physical addresses. The provision of an address translation cache is useful in improving performance by reducing the number of slow page table walks to memory required in order to obtain the required address translation data.
It is also known to provide the address translation cache as a set associative structure. When a new item of address translation data is to be allocated into the set associative address translation cache, a number of bits of an associated virtual address can be used to form an index to identify a particular set within the address translation cache, with the address translation data then being stored within one of the entries of that set. The actual bits of the virtual address used to form the index will depend on the page size in memory associated with the address translation data.
When the associated processing circuitry that is using the address translation cache is arranged to execute multiple items of supervised software under the control of a supervising element, as for example is the case when a supervising element in the form of a hypervisor controls the operation of multiple guest operating systems, the address translation data can be obtained using a multi-stage translation process, where a first stage is managed by an item of supervised software and a second stage is managed by the supervising element. When employing such a process, the stage one page size may not be the same as the stage two page size, and the allocation of the address translation data into the address translation cache will take place based on whichever of those two page sizes is the smaller. This can cause issues when a page invalidate request associated with an item of supervised software is to be handled, in situations where the first stage page size exceeds the second stage page size (referred to herein as a splinter condition). In particular, in such a case it will not typically be possible for the maintenance circuitry to ascertain where the relevant address translation data will have been stored within the address translation cache, and accordingly it is typically necessary to scan the entire address translation cache to determine the entries that need to be invalidated. This can significantly impact performance.
Accordingly, it would be desirable to provide an improved mechanism for handling the performance of page invalidate requests in the presence of such a splinter condition.